1. Field of the Invention
The present invention relates to semiconductor devices and their manufacturing method. In particular, the present invention relates to MOS transistors requiring silicide protection and their manufacturing method.
2. Description of the Background Art
In transistors used for logic LSI (large-scale integrated circuit), the reduction in the parasitic resistance of source and drain regions and the wiring resistance of a polysilicon gate electrode at the same time is effected by Salicide (self-aligned silicide) technology in which a silicide film is selectively formed in a self-aligned manner on the surfaces of a source/drain layer and a polysilicon gate electrode.
Silicide film have the advantage of reducing the parasitic resistance and wiring resistance, however, in some cases the presence of silicide film causes an unfavorable phenomenon. To avoid such a phenomenon, portion whereat formation of silicide film is not desirable is protected by a silicide protection film that prevents a silicide film formation.
The problem in forming silicide film and silicide protection film is discussed herebelow. As an example of semiconductor integrated circuits, an inverter circuit C2 and a protection circuit C1 protecting it are shown in FIG. 35.
In the protection circuit C1, a P channel MOS transistor P1 and an N channel MOS transistor N1 are connected in series and an input pad PD is connected to a node ND1 connecting the transistors P1 and N1. The gate electrode of the transistor P1 is connected to a power supply potential (Vcc) and is normally in OFF state. The gate electrode of the transistor N1 is connected to a ground potential and is normally in OFF state.
In the inverter circuit C2, a P channel MOS transistor P2 and an N channel MOS transistor N2 are connected in series and a node ND2 connecting the transistors P2 and N2 is connected to another circuit (not shown). The gate electrodes of the transistors P2 and N2 are connected to the node ND1 of the protection circuit C1.
Here, suppose a surge voltage is inputted through the input pad PD, i.e., where ESD (Electro Static Discharge) occurs. The surge voltage is far higher than the operating voltages of normal MOS transistors. Therefore, in the absence of the protection circuit C1, the surge voltage will be applied to the gate electrodes of the P channel MOS transistor P2 and the N channel MOS transistor N2 in the inverter circuit C2 to possibly dielectric breakdown of both the gate insulatings. However, when a surge voltage is applied, the presence of the protection circuit C1 causes a breakdown between the source and drain of the transistors P1 and N1 so that the current flows, which prevent the surge voltage being applied to the inverter circuit C2.
However, when a very large surge voltage is applied to between the source and drain in the protection circuit C1, the P channel MOS transistor P1 or the N channel MOS transistor N1 in the circuit C1 will be destroy. The surge voltage at this time of destroy is called as ESD resistance, and it is desirable to design its value as large as possible. But if a silicide film is formed on the surface of the source and drain layer, the ESD resistance might be lowered.
FIG. 36 shows a plane construction of an MOS transistor M1. The MOS transistor M1 comprises a slender gate electrode GE provided in the center, and a source/drain layer SD on its both sides in the shorter direction, and a suicide film SF formed on the surface of the source/drain layer SD.
FIG. 37 is an enlarged view of the area A of FIG. 36. Generally, the silicide film SF is polycristal construction and comprises large and small silicide crystal grains GR, as shown in FIG. 37. Accordingly, each grain shape is reflected in the grain boundaries to exhibit corrugations. This is true for the edge portion of the silicide film SF along with the edge portion of the gate electrode GE. As shown in FIG. 37, crystal grains GR face one another across the gate electrode GE. When a surge voltage is applied to such a structure, the surge current is concentrated between the projections (i.e., space indicated by two arrows in opposite directions) of the crystal grains GR on both sides of the gate electrode GE and, in such portions, the intensive breakage occurs. This makes the MOS transistor inoperative, failing to function as a protection circuit. For this reason, silicide film in not formed on the surface of the source/drain layer in the protection circuit, and a silicide protection film is formed instead.
With reference to FIG. 38, the construction of an MOS transistor M2 with a silicide protection film is described herebelow.
As shown in FIG. 38, a silicide protection film SP comprising a silicon oxide film (SiO.sub.2) is formed on the surfaces of a gate electrode GE and of a source/drain layer SD in the vicinity of the gate electrode GE while no silicide film SF is formed over the silicide protection film SP. This construction allows to increase the distance between the edge of the silicide film SF and the edge of the gate electrode GE. Even if the edge of the suicide film SF is in the shape of a continuous corrugation and hence a surge voltage tends to concentrate on projected portions, the surge current will be dispersed because it must pass a long distance through a lightly doped drain region (not shown) and a source/drain layer. Still further, when it passes through the lightly doped drain region having a relatively high resistance, a voltage drop and the like occur and thus prevents the MOS transistor from being broken.
As described above, the silicide protection film SP has been used to protect a silicide film SF formation in MOS transistors in which its formation can cause disadvantages.
In the formation of a silicide protection film SP, a silicon oxide film is formed over the entire surface of a silicon substrate SB and the silicon oxide film is then selectively removed by dry etching, such as RIE (Reactive Ion Etching), to form the silicide protection film SP only on the surfaces of a gate electrode GE and of a source/drain layer SD in the vicinity of the gate electrode GE.
Referring to FIGS. 39 and 40 that are a cross-sectional view of a MOS transistor at a processing step subsequent to the silicide protection film SP formation, the problems resulting from the formation of the silicide protection film are discussed herein.
With reference to FIG. 39, over an SOI substrate SI, there are a protection region PR in which a plurality of MOS transistors M1 requiring a silicide protection film will be formed and a normal region OR in which a plurality of MOS transistors M2 requiring no silicide protection film will be formed. The SOI substrate SI comprises a silicon substrate SB, a buried insulating layer BO, and an SOI layer SL, which are formed in this order on the substrate SB.
In the normal region OR a silicide film SF is formed over a source/drain layer SD2 and a gate electrode GE2, whereas in the protection region PR a silicide protection film SP of oxide film is formed over the entire surface and there are no silicide film SF over a source/drain layer SD1 and a gate electrode GE1.
After forming the silicide film SF and the silicide protection film SP, an interlayer insulating film IZ is formed over the SOI substrate SI. Thereafter, as shown in FIG. 40, contact holes CH1 and CH2 are formed so as extends through the interlayer insulating film IZ to reach the source/drain layers SD1 and SD2, respectively.
The problem at this time is that the selective ratio of etching differs between the silicide film SF and the silicide protection film SP. That is, since the silicide protection film SP being oxide film is more easily etched than the silicide film SF, if formed the contact holes CH1 and CH2 at the same time, the contact hole CH1 results in somewhat over-etching or in some cases it extends through the SOI layer to reach the buried insulating layer BO, failing to function as an MOS transistor.
As described earlier, to avoid the breakdown of MOS transistors by a surge voltage, a voltage drop due to a high resistance layer, e.g., a lightly doped drain layer, is effective. However, almost all part beneath the silicide protection film SP arc occupied by the source/drain layer and even the source/drain layer SD1 on which no silicide film SF is present has a sheet resistance of about several hundred .OMEGA./.quadrature.. In order to expect a voltage drop in surge voltage, it is therefore necessary to form a source/drain layer SD1 that is covered with a silicide protection film SP over a wide area. This is negative toward device downsizing.